1. Field of the Invention
The present invention relates generally to integrated circuit chip package technology and, more particularly, to an increased capacity QFP semiconductor package which includes exposed leads and an exposed die pad on the bottom surface of the package body thereof, and further includes one or more integrated passive components or devices to enhance electrical performance and reduce the number of component parts needed on an underlying printed circuit board or motherboard.
2. Description of the Related Art
Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or system board. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.
The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die pad of the leadframe also remains exposed within the package body.
One type of semiconductor package commonly known in the electronics field is referred to as a quad flat pack (QFP) package. A typical QFP package comprises a thin, generally square package body defining four peripheral sides of substantially equal length. Protruding from each of the four peripheral sides of the package body are a plurality of leads which each have a generally gull-wing configuration. Portions of the leads are internal to the package body, and are electrically connected to respective ones of the pads or terminals of a semiconductor die also encapsulated within the package body. The semiconductor die is itself mounted to a die pad of the QFP package leadframe. In certain types of QFP packages referred to as QFP exposed pad packages, one surface of the die pad is exposed within the bottom surface of the package body.
In the electronics industry and, in particular, in high frequency applications such hard disk drives, digital televisions and other consumer electronics, there is an increasing need for QFP exposed pad packages of increased functional capacity, coupled with reduced size and weight. In this regard, with recent trends toward high integration and high performance semiconductor dies, there is a need for QFP packages which have a larger number of I/O's with excellent thermal and electrical properties, yet are of minimal size so as not to occupy the limited space available on an underlying PCB. In an attempt to address these needs, Applicant has developed the semiconductor packages described in co-pending U.S. patent application Ser. Nos. 11/425,505 and 11/775,566, the disclosures of which are incorporated herein by reference. The present invention comprises an enhancement to the semiconductor package designs described in the aforementioned co-pending patent applications of Applicant. More particularly, the semiconductor device or package of the present invention includes one or more integrated passive components or devices which is/are operative to enhance the electrical performance of the semiconductor package, while at the same time reducing the number of component parts that must be included on the underlying PCB or motherboard. Though it is known in the prior art to integrate passive components into laminate and leadframe based semiconductor packages, none of the existing integration methods result in a semiconductor package configuration wherein at least one pad is provided on the semiconductor package and dedicated to the passive component for connectivity purposes. In addition, the design attributes of the semiconductor package of the present invention provide the freedom to change circuit topology without changing the semiconductor package design, thus helping circuit designers to change passive component interconnections on the motherboard without changing passive interconnection in the semiconductor package. These, as well as other features and attributes of the present invention will be discussed in more detail below.